The present invention is directed, in general, to a semiconductor device.
This application is a continuation of 09/572,060 May 17, 2000 which claims benefit of 60/168,911 Dec. 3, 1999.
Semiconductor devices are continually improved to enhance device performance. For example, both smaller device size and higher speed of operation are highly desirable performance targets. Transistors also have been continually reduced in size as the ability to construct smaller gate structures for complementary metal oxide silicon (CMOS) transistors has improved. With the smaller gate structures, the gate dielectric thickness has also substantially decreased to 3 nm and below in today""s current technologies. Polysilicon is one material used to form these gate structures. However, the use of polysilicon gates, particularly in smaller CMOS devices, has caused several problems. A significant disadvantage is the polysilicon depletion effect. The polysilicon depletion effect occurs because polysilicon does not have an infinite amount of carriers. Presently, polysilicon can only be doped to a range of about 2E20/cm3 to about 3E20/cm3. As such, an infinite amount of carriers (for all intents and purposes larger than about 5E21/cm3) are not present in the gate material, and when the gate is biased, a depletion region near the polysilicon gate/gate dielectric interface is generated due to the lack of these carriers.
If the polysilicon gate is not implanted to a high enough concentration, or if the implanted dopant is not sufficiently activated, a significant voltage is dropped across the gate. When the active carrier concentration in the polysilicon is not high enough so that the Fermi level at the polysilicon/gate dielectric interface, such as silicon dioxide, the band bending in the poly silicon becomes voltage-dependent. As the device is biased such that the silicon substrate is inverted and a channel is formed, the polysilicon gate becomes depleted of free carriers. As the polysilicon is driven into depletion, part of the applied voltage is dropped across the gate, reducing the field at the Si/SiO2 interface and decreasing the channel carrier concentration. As a result, the drive current is reduced, thereby reducing the device""s switching speed as well.
As the gate dielectric has scaled to below 3 nm, effects attributable to polysilicon depletion, as discussed above, are even more acute. The polysilicon depletion effect makes the gate dielectric to appear electrically thicker than it actually is. For example, the polysilicon depletion effect causes the gate oxide to electrically function as if it were from about 0.5 nm to about 1.5 nm thicker than the actual gate oxide thickness. When the gate dielectric is on the order of 15 nm thick, 0.5 nm of additional thickness due to the silicon depletion effect is not significant. However, when the gate dielectric thickness is about 5 nm and below, an additional operational thickness of 0.5 nm due to the polysilicon depletion effect can have a significant impact on the device""s operation and performance as discussed above. Additionally, another difficulty is that with the scaling of devices, thermal treatments are also limited (i.e., thermal budgets are reduced). Therefore, the polysilicon may be doped heavily, e.g., 2-3E20/cm3, but the dopants are difficult to electrically activate due to these reduced thermal budgets.
Since polysilicon material cannot be doped or dopants activated at levels higher than about 2-3E20/cm, scaling the gate length produces a gate resistance. Therefore, a higher than desirable electrical sheet resistance or resistivity for polysilicon arises and produces unacceptable large time delays in the circuits due to the RC time constant formed.
Another problem encountered with polysilicon gate is lateral diffusion. Often, gate dopants diffuse laterally into a neighboring counter-doped gate, which can cause the gate to malfunction.
The use of p-type polysilicon gates was first introduced to reduce short-channel effects and lower threshold voltage as the devices were pushed into the submicron regime. However, with the use of boron as the dopant for the p-type polysilicon gates, dopant diffusion and its subsequent penetration into the gate dielectric have become a problem. The penetration of the boron into the gate dielectric causes a number of problems not only with the quality of the dielectric but also with the device operation. Boron penetration shifts the threshold voltage of the metal oxide semiconductor (MOS) devices to more positive values. Degradation of the metal oxide semiconductor field effect transistor (MOSFET) transconductance and the subthreshold slope is also correlated with boron penetration.
Accordingly, what is needed in the art is a semiconductor device that has gate structures that address the problems discussed above.
To address the above-discussed deficiencies of the prior art, the present invention provides a semiconductor device disposed over a semiconductor substrate having opposite types of first and second transistors formed thereon. In an exemplary embodiment, the device includes a first gate electrode that includes a first gate electrode material having a work function compatible with the first transistor, and a second gate electrode that includes a second gate electrode material having a work function compatible with the second transistor and the first gate electrode material, which forms a gate stack.